Design of Low power, Low Jitter Ring Oscillator Using 50nm CMOS Technology
نویسنده
چکیده
A modif ied ring oscillator presented in this paper. The voltage control oscillator is designed and simulated in 50nm CMOS technology. The frequency of oscillation of the VCO is 2.6GHz with 0.064 mW power dissipation and the center drain current of 64uA is us ed. Tuning range is of 72% and the jitter is of 39.8pS. Index Terms Voltage Controlled Oscillator (VCO), power dissipation, jitter, tuning range, phase locked loop (PLL) —————————— —————————
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